Staff Engineer, AI/ML for Circuit Design

Samsung Semiconductor10 months ago
San Jose, CA, United States
On-site
Full-time
Junior Level (1-3 years)

Job Description

Position Overview

Samsung Display Lab is seeking an AI expert to join a dynamic team at the forefront of integrating machine learning with advanced chip design for OLED and next-generation displays. In this role, you will collaborate with researchers and engineers to drive AI-assisted panel layout, develop high-fidelity surrogate models for parasitic capacitance prediction, and optimize pixel circuit designs. Work onsite in San Jose, CA as part of a global leader committed to innovation, inclusion, and excellence.

Key Responsibilities

  • Develop EDA design workflows for pixel circuits for OLEDs
  • Create automatic scripts for schematic generation and layout assembly
  • Apply Reinforcement Learning and/or Diffusion models for placement & routing and evaluate against classical algorithms
  • Build AI-based surrogate models for parasitic capacitance extraction
  • Utilize Graph Neural Networks (GNN) for circuit design and parameter estimation
  • Leverage design of experiments (DoE) and optimization methods to accelerate simulation and tuning
  • Develop optimization algorithms for pixel array compaction and contribute to continuous improvement via active learning

Required Qualifications

  • BS in Computer Science (5+ years experience) or MS in Computer Science (3+ years) or a PhD in Electrical Engineering/Computer Engineering/Applied Physics (or equivalent)
  • Proficiency with SPICE/Spectre/HSPICE, Cadence Virtuoso/ADE, layout design, and parasitic extraction
  • Strong Python skills and ML fundamentals (experience with PyTorch or TensorFlow, scikit-learn, NumPy, Pandas)
  • Proven experience in building and validating surrogate models along with multi-objective optimization
  • Hands-on experience with Reinforcement Learning, Diffusion models, and Graph Neural Networks (GNN)
  • Working knowledge of EDA tools for layout assembly, placement & routing, parasitic extraction, and pixel circuit compaction
  • Solid understanding of classical algorithms for placement and routing in chip design
  • Publications or patents in display technology, EDA, or ML-for-hardware are a plus
  • Strong analog/digital circuit fundamentals with hands-on OLED pixel/gate driver design experience
  • Excellent collaboration skills, adaptability, and a genuine passion for innovation and learning

Benefits & Perks

  • Compensation: Base Pay Range of $157,000—$243,000 USD (individual pay depends on skills and experience)
  • Competitive incentive opportunities rewarding individual and company performance
  • Paid Time Off: 4+ weeks of paid time off per year, plus holidays and sick leave
  • Family Care: Support including stipends for fertility care or adoption, medical travel support, and virtual vet care
  • Emotional Wellness: Access to on-demand apps and free confidential therapy sessions
  • Onsite amenities such as a café and gym, along with virtual fitness classes
  • A flexible work environment to help manage work-life balance
  • Opportunities for charitable giving matches and community involvement

Required Skills

SPICE/Spectre/HSPICE
Reinforcement Learning
Machine Learning
Circuit Design
Cadence Virtuoso
EDA
PyTorch
TensorFlow
Optimization Algorithms
Parasitic Capacitance Extraction
Graph Neural Networks (GNN)
Python
Layout Assembly
Diffusion Models