Senior Analog/Mixed-Signal Layout Designer

Location: Austin, USA

Status: Active

Salary Range: USD 180,000 – 200,000

Experience: 10–15 Years

Job Description

We are seeking an experienced Analog/Mixed-Signal Layout Engineer to drive the physical layout of high-performance ADC/DAC, SerDes, and mixed-signal circuits in advanced technology nodes (2nm–16nm). This role requires deep technical expertise, strong collaboration with circuit design teams, and the ability to deliver high-quality layouts that meet aggressive PPA and manufacturability goals.

Key Responsibilities

• Lead the physical layout development for cutting-edge ADC/DAC, SerDes, and analog/mixed-signal circuits across advanced nodes (2nm–16nm).
• Plan and execute layouts for high-speed, low-noise analog blocks with an emphasis on matching, symmetry, signal integrity, and optimal parasitic performance.
• Work closely with circuit designers to meet challenging power, performance, and area (PPA) targets while ensuring DFM compliance.
• Utilize Cadence Virtuoso and Synopsys verification tools for layout creation, verification, and integration.
• Drive floorplanning, block partitioning, power grid design, guard ring placement, and substrate isolation strategies.
• Collaborate with foundry and CAD teams to enhance flows for TSMC FinFET and Gate-All-Around (GAA) nodes.
• Perform and close verification checks, including LVS, DRC, ERC, and parasitic extraction (PEX).
• Support top-level integration and tape-out, ensuring complete, signoff-ready layout data and GDS handoffs.
• Mentor junior engineers and contribute to layout methodologies, productivity improvements, and automation initiatives.

Must Have Qualifications

• 10+ years in analog/mixed-signal layout across advanced nodes (2nm–16nm; TSMC preferred).
• Strong layout experience with high-speed ADC/DAC and SerDes, including timing, matching, shielding, and EM.
• Proficient with Cadence Virtuoso (Layout, XL, PVS, Quantus) and full schematic-to-layout flow.
• Hands-on experience with FinFET and/or GAA technologies.
• Solid knowledge of key analog layout structures (current mirrors, differential pairs, capacitors, resistors, guard rings, ESD).
• Proven tape-out experience, including signoff checks and documentation.
• Strong analytical, communication, and problem-solving skills.
• Self-driven and effective in fast-paced start-up environments.
• Experience with Calibre tools and scripting (Skill/Python/Tcl).
• Exposure to mixed-signal SoC floorplanning and top-level integration.

Understanding

Understanding of SI, IR-drop, and thermal optimization in high-speed designs.