Infinity Fabric Verification Staff Engineer

Position Overview

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers to PCs, gaming, and embedded systems. Our culture of innovation, collaboration, and bold ideas drives us to push the limits in solving the world’s most important challenges. As part of the Infinity Fabric transport layer verification team, you will serve as a primary pre-silicon verification engineer responsible for verifying configurable switches and die-to-die interconnect, a critical component available in every new AMD product across AI, Client, Server, Graphics, and Semi-Custom markets. In this role, you will work closely with architects, RTL designers, performance engineers, and post-silicon validation engineers while mentoring junior engineers.

Location: Austin, TX

Key Responsibilities:

• Create project schedules and staging plans for new feature development.
• Develop and enhance SystemVerilog/UVM-based testbenches to verify new features for AI and Server products.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
• Lead a team of verification engineers in the execution of test plans within established project schedules.
• Communicate with project management to align new feature development with the overall Infinity Fabric roadmap.
• Mentor verification engineers to build a high-performing team.

Required Qualifications:

• Proven experience verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologies.
• Demonstrated ability to create and execute comprehensive test plans in collaboration with design and verification teams.
• Track record of technical leadership in silicon design and verification closure.

Preferred Qualifications:

• Extensive industry experience and a strong foundation in Systems & SoC architecture, with expertise in areas such as CPU or GPU, memory sub-systems, fabrics, CPU/GPU coherency, multimedia, or I/O subsystems.
• Experience architecting and developing complex verification environments in SystemVerilog or C++, including scripting with Perl, Ruby, Make, or similar tools.
• Hands-on experience in implementing verification tests, sequences, scoreboards, checkers, assertions, and coverage groups.
• Proven leadership in driving complete verification processes, including coverage closure and bug tracking.
• Exposure to RTL design, software development, formal verification, or related domains.
• Excellent communication, management, and presentation skills.
• Education: Master’s degree in a related discipline preferred.

Benefits & Perks

• Benefits: AMD benefits at a glance.