Physical Design Engineer - DSP Team

Position Overview

Qualcomm Technologies, Inc. is a leading technology innovator that pushes the boundaries of what's possible to enable next‐generation experiences in a smarter, connected future. In this role, you will work on activities related to Synthesis, structured placement, clock tree synthesis (CTS), and overall physical design convergence deliverables – driving custom designs to achieve higher performance while containing overall power.

Key Responsibilities

• Update the physical implementation flows for optimum PPA (power, performance, and area)
• Drive the development of semi-custom design techniques to maximize utilization, performance, and power efficiency
• Use and extend/enhance design methodologies through scripting to achieve the best PPA
• Collaborate independently with minimal supervision between physical design and logic teams
• Communicate complex technical information effectively to diverse audiences, requiring strong negotiation and influence skills
• Contribute to key organizational decisions and provide input to senior leadership
• Tackle undefined tasks requiring multiple mental approaches while maintaining high quality to avoid rework
• Innovate new processes and procedures within guidelines to achieve established objectives
• Apply deductive and inductive problem solving with advanced data analysis and interpretation skills
• Utilize tools (e.g., Fusion Compiler) to execute advanced architecture and design of complex blocks and suggest design protocol improvements
• Run advanced power checks on multiple blocks, making recommendations when specifications are not met

Required Qualifications

• Bachelor's degree in Science, Engineering, or a related field; alternatively, a Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering with 8+ years of relevant work experience, a Master's degree with 7+ years, or a PhD with 6+ years
• 12+ years of ASIC Physical Design, Synthesis, or related work experience
• Strong proficiency in P&R, timing analysis, and CAD tools (e.g., Synopsys FC/DC, ICC2 or Cadence Genus, Innovus)
• Excellent understanding of logic optimization for high-speed design implementation, clock structures, and power optimization
• 2+ years of experience with high-performance microprocessor design

Preferred Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering
• 15+ years of CPU or GPU design or related work experience
• 10+ years of experience with architecture and design tools
• 10+ years of experience with scripting tools and programming languages

Benefits & Perks

• Compensation: $211,200.00 - $316,800.00
• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants (note: employees on sales-incentive plans are not eligible for the annual bonus)
• Highly competitive benefits package designed to support success at work, at home, and at play