Staff Engineer, AI/ML for Chip Design

Position Overview

Advancing the World's Technology Together – our technology solutions power the tools you use every day, including smartphones, electric vehicles, hyperscale data centers, and IoT devices. At Samsung Display Lab, we are at the forefront of applying machine learning in display production and R&D. We are hiring an AI expert with a background in circuit/pixel layout design and circuit simulation by fusing physics‐based simulation with modern AI/ML. In this role, you will drive AI‐assisted panel layout, architect pixel/backplane circuits, and build high‐fidelity surrogates for parasitics using AI. Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

Key Responsibilities

AI for design & optimization:

• Develop physics-informed ML and GNN surrogates mapping layout/process to electrical KPIs.
• Run multi-objective optimization via Bayesian optimization/evolutionary search; generate candidate pixel and driver topologies.
• Apply RL for process control and compensation strategy tuning.

Circuit Simulation:

• Compose fast design loops that combine Layout/SPICE with learned surrogates to accelerate what-if sweeps.
• Build data/feature pipelines from fab/test and panel bring-up; implement active learning and uncertainty quantification.

Required Qualifications

• BS in Computer Science (or equivalent) with 10+ years experience; MS with 8+ years; or PhD with 5+ years in Electrical Engineering, Computer Engineering, Applied Physics, or related fields.
• Proficiency with SPICE/Spectre/HSPICE, Cadence Virtuoso/ADE, including layout and parasitic extraction.
• Strong Python and machine learning fundamentals using frameworks such as PyTorch or TensorFlow, along with scikit-learn, NumPy, and Pandas.
• Experience building and validating surrogate models and running multi-objective optimization.
• Hands-on experience with GNNs for layout-to-electrical mapping, PINNs/physics-informed ML, or differentiable simulation.
• Expertise in reinforcement learning for control/parameter tuning, Bayesian optimization at scale, and DoE/active learning.
• Documented publications or patents in display, EDA, or ML-for-hardware fields.
• Solid analog/digital circuit fundamentals with hands-on OLED pixel/gate driver design experience.
• Demonstrated ability to transition designs from simulation to hardware bring-up and achieve correlation.
• An inclusive disposition with adaptability to diverse global norms.
• Avid learner with a curious and resilient approach to challenges.
• Collaborative mindset with the ability to build supportive relationships.
• Innovative and creative, proactively exploring new ideas and adapting to change swiftly.