Senior IC Design Engineer
Palma Ceia SemiDesignabout 2 months ago
McKinney, TX, United States
On-site
Full-time
Junior Level (1-3 years)
Job Description
Required:
- Deep experience in IC design leading to production, production debug, testing support and yield enhancement
- Experience with RF system architectures, link budgets, trade-offs for key elements such as DC offset calibration loop, IIP2 calibration loop, AGC, etc.
- RF or analog circuit design for WiFi, LTE, TV or other high dynamic range systems
- Implementation experience in either 65nm or 40nm
- At least 7 years at a relevant comm IC house or IDM
Big Plus:
- Experience with leading a team from design concept through project completion
- Lab and testing experience: spurious debug, noise testing, performance testing
- Customer-facing exposure: determining specifications, schedule, technical trade-offs
Block Experience (one or more would be required):
- LNA, Mixer, VGA, PA driver, IQ modulatorActive filter design,
- Active filter design, high speed op-amp, log limiter amplifiers, power detection
- PLL, integer/fractional loops, PFD,
- PLL, integer/fractional loops, PFD, high speed divider circuits, VCO, loop filter, PLL system analysis, timing analysis, pre-scalers,
- High speed DAC design, above 10 bit, above 300MSPS
- High speed DAC design, above 10 bit, above 300MSPS
- High speed ADC design, (one of or all — pipeline,
- High speed ADC design, (one of or all — pipeline, SAR and CTSD), above 10 bit, above 80MSPS
Location:
Location: McKinney, Texas (preferred)
Additional Information:
- Start Date: Immediate
- Email resumes to: careers@pcsemi.com.
- No calls. EOE.
Required Skills
IQ modulator
high dynamic range systems
team leadership
WiFi
timing analysis
IC design
SAR
noise testing
production debug
40nm technology
link budgets
high speed op-amp
high speed DAC design
specifications determination
PLL design
DC offset calibration loop
VGA
65nm technology
yield enhancement
Mixer
schedule management
LTE
LNA
active filter design
spurious debug
testing support
RF system architectures
technical trade-offs
AGC
log limiter amplifiers
performance testing
power detection
RF circuit design
CTSD
customer-facing exposure
pipeline encoding
high speed ADC design
PA driver
IIP2 calibration loop