ASIC Design Engineer

Position Overview

Amazon Devices is an inventive research and development company that designs and develops high-profile devices such as the Kindle, Fire Tablets, Alexa, Fire TV, Health Wellness, Amazon Echo, and Astro products. This is an exciting opportunity to join Amazon in developing its next generation SOC’s for machine learning enabled consumer products. We are looking for exceptional engineers and engineering leaders to join our SOC development team and help develop the next generation of chips based on a revolutionary architecture. The team that built the innovative Silicon IP AZ1 Neural Edge powering the latest generation of Echo devices is seeking a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers. Work hard. Have Fun. Make history.

Key Responsibilities

In this role, you will develop SoCs to be deployed in a range of Amazon devices by integrating industry standard and custom hardware IP and subsystems. You will work closely with System Architects, SoC architects, IP developers, and physical design teams to meet power, performance, and area goals. You will also help define processes, methods, and tools for designing and implementing large, complex SoCs, including developing chip-level and subsystem-level netlists that integrate various IPs.

• Work with Chip Architects to understand architecture and high-level product requirements.
• Convert Chip specifications into RTL using internal and external IPs.
• Review architecture and design of custom IPs for integration into SOCs.
• Design & Develop RTL for Interfaces, Power Management, Clocking, Reset, Test & Debug.
• Develop and implement methodologies for I/O, DFT, Debug, Clocking, and Power Management.
• Provide technical leadership through leading by example, mentorship, and strong teamwork.

Required Qualifications

• BS degree or higher in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS).
• 5+ years of practical semiconductor design experience including full-chip and subsystem RTL integration.
• Experience in micro-architecture definition from architecture guidelines and model analysis.
• Proficiency in RTL coding (Verilog/System Verilog) and debugging along with performance, power, and area trade-off analysis.
• Experience in closing full-chip and subsystem timing with synthesis and static timing analysis teams.
• Familiarity with DFT tools for scan and BIST insertion.
• Excellent verbal and written communication skills, collaboration, and teamwork with an ability to contribute to diverse and inclusive teams.

Preferred Qualifications

• MS or PhD degree in Computer Engineering, Electrical Engineering, or a related field.
• Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SOC bus architectures, Arteris NOC interconnect, ARM’s AXI/AHB bus architecture & protocols, and serial interfaces such as PCIe, QSPI, I2C, UART, EMMC, and USB. Experience with LPDDR controllers, embedded memory (SRAM, OTP, etc.), and other IP integrations such as ADC, PLL, DLL, PVT sensors, GPIO & Debug (Coresight) is also desired.
• In-depth knowledge in one or more areas such as CPU, DSP, or programmable accelerators.
• SOC bring-up and post-silicon validation experience.
• Experience with early RTL power analysis.
• Experience with gate-level testing and multi-clock design practices.
• Successful tape outs of complex, high-volume SoCs in advanced design nodes.
• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance, and area.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.